Conventionally, a plurality of bumps are disposed on the surface of a semiconductor device, then flipped to an external substrate. For example, a driver IC chip having bumps is flipped and bonded to a glass substrate or a COF film. Especially, during the manufacture of the panels of STN LCD, a layer of SiO2 is evaporated on the surface of the glass substrate then a layer of ITO conductive traces are patterned and formed by sputtering and photolithography. Normally the glass substrate is called ITO conductive glass. Another glass is attached to the ITO conductive glass then the gap between two glasses is filled with liquid crystals. To assemble a display panel, a plurality of driver IC chips with a plurality of bumps are needed to bond to the ITO conductive glass for driving the panel. However, the chip dimension is getting smaller and smaller, the number of bumps on chips are getting more and more. Therefore, the pitch between the bumps has to be reduced, i.e., the bump widths and bump spacing have to be reduced. Without well-controlled bump spacing, electrical shorts between bumps become a serious issue when implementing ACF or soldering for flip-chip electrical connections. With the reduced bump pitch and the minimum requirement of bump spacing, the bump width becomes smaller where the top surface of bumps available for test probing become smaller as well, which can not be probed by the probes of a probe card leading to testing failure.
As shown in FIGS. 1 and 2, a conventional semiconductor device 100 comprises a chip 110 and a plurality of bumps 120 disposed at a same row where the bumps 120 are disposed on the surface 111 of the chip 110 and are electrically connected to the bonding pads 112 thereunder. A plurality of probing points 121 for probing are defined on the top surfaces of the bumps 120 where the probing points 121 are disposed in a line. According to the processing capabilities and product specifications, when the bump spacing S1 of the same row of bumps is below 10 μm, electrical shorts and insufficient bonding strength become the major issues. When the bump widths W1 of the same row of bumps is below 15 μm, the tolerance of the defined probing points 121 becomes smaller, i.e., probes can not touch all the bumps at the same time during probing. Therefore, the bump pitch of the same row of bumps can not further be reduced.
A conventional way of solving the current issue is to dispose a row of bumps into a plurality of rows of bumps to enable staggered probing by redistribution traces done on a chip. An additional passivation layer on chip is also required. Moreover, the bonded substrate is designed to have multiple layers of traces. The chip having RDL and the multi-layer substrate are different from conventional STN flip-chip structure, an extra expensive cost is expected.